1. Field of the Invention
The present invention relates to a method for forming a coating film upon a surface of a semiconductor wafer, a glass substrate or the like.
2. Description of Prior Art
Demands for high integration of semiconductor devices are constantly increasing and a new generation of 0.15 μm gate lengths is now here. For such cases, it is known that improvement can be obtained in the properties of semiconductor devices by using Cu as wiring material, in place of conventional Al. That is, since Cu, has superior tolerance or resistance to EM (electro-migration), compared to Al, a low electrical resistance enables to reduce a signal delay or a decrease in level due to a wiring resistance. Therefore, it can be used under high current density. Specifically, by using this, the permissible current density can be released or enlarged up to three times, and the wiring width can also be made fine or minute.
However, compared to Al, it is difficult to control the etching rate of Cu. Therefore, attention is being paid to a copper damascene method as a means for realizing multi-layer Cu, but without the necessity of Cu etching.
Explanation will be given of the copper damascene method by referring to FIGS. 1(a) through 1(h).
First, as shown in FIG. 1(a), an interlayer isolation film of SiO2, SOG, or the like is formed on a substrate by a CVD method, and on this film is provided a patterned resist mask. As shown in FIG. 1(b), wiring gutters are formed by selective etching and removal of the resist mask. Next, as shown in FIG. 1(c), a barrier metal is accumulated thereon, and as shown in FIG. 1(d), Cu is buried or filled into the wiring gutters by means of an electrolytic plating or such so as to form a lower layer wiring. Then, after polishing the barrier metal and Cu by means of CMP (chemical polishing), another interlayer insulation film is formed thereon as shown in FIG. 1(e). The interlayer insulation film is etched selectively through the resist mask, on which a pattern is formed, in the same manner, thereby forming (dual damascening) via-holes (contact holes) and trench holes (gutters for the upper layer wiring) in the interlayer insulation film as shown in FIG. 1(f). As shown in FIG. 1(g), a barrier metal is accumulated on the walls of the via-holes and the gutters for the upper layer wiring, and as shown in FIG. 1(h), Cu is buried or filled into the via-holes and the gutters for the upper layer wiring, such as by the electrolytic plating method, thereby forming the upper layer wiring.
As mentioned above, when forming a multi-layer wiring by means of the copper damascene method, it is essential to increase an aspect ratio (height/width) of the via-holes in order to obtain a minute wiring. Also, a low dielectric constant of the interlayer insulation film is required.
Studies were then conducted on the use of organic or inorganic SOG with low dielectric constants (ε=3.5 or less). However, even if the multi-layer wiring is formed by using this kind of SOG through the copper damascene method, the dielectric constant of the SOG comes to be higher than it is by nature after forming the multi-layer wiring.